Current clock recovery structures for high speed links use a minimum likelihood method for optimizing the sampling of incoming data. Such clock recovery structures are described in Electronic Letters, J. D. H. Alexander, “Clock Recovery from Random Binary Signals,” vol. 11, pp. 541-542, October 1975, which is hereby incorporated by reference. The type of phase detector and clock recovery circuit described by Alexander is widely used. As long as the jitter on the input data has a symmetric probability distribution, the technique and circuitry described by Alexander works well.
FIG. 1 illustrates one embodiment of a clock recovery circuit 50 consistent with Alexander's teachings, with modifications on the input for receipt of a differential input signal. Clock recovery circuits such as circuit 50 are used in a receiver device to determine the optimal time to sample differential input data at 52 and 54 in order to avoid sampling data during data transitions. This circuitry is used because the receiving device has no knowledge of the relative delay between its clock input and the data from the transmitting device. Circuit 50 uses a separate master clock 58 whose frequency is similar or identical to the clock used to clock the transmitted data. A feedback loop makes adjustments to the clock so that the receiving circuitry functions correctly.
The input data at 52 and 54 are shown as differential (as most high speed links are). The data are processed by a pair of limiters 60 and 62 to reshape the data. The data are then sampled by two latches 64 and 66, whose clocks are ck_edge and ck_center. Ck_edge and ck_center are generated by two delay interpolators shown together as 70. These delay interpolators move the location of the ck_edge and ck_center clocks based on the value of their respective delay_codes (delay_code_edge 72 and delay_code_center 74) which are output from filter 76. The interpolators allow an all-digital implementation of the clock recovery loop because the digital codes change the delay of the output clocks in fine increments.
The logic in the feedback loop is designed to change delay_code_edge 72 so that ck_edge is aligned with a most likely data transition time (i.e., the worst time to try and sample correct data). Ck_center is created by digitally manipulating delay_code_center 74 as a function of delay_code edge 72 so that ck_center is one half of a data bit period (half of the clock cycle) away from ck_edge. This placement of ck_center is near optimal if the placement of ck_edge corresponds to the center of symmetrical jitter in the input data eye diagram. The Alexander reference describes one embodiment of the logic functions used in the early/late logic 80. This logic determines whether ck_edge and ck_center are early, late or neither. The filter 78 then produces signals 72 and 74 which adjust ck_edge and ck_center. These signals 72 and 74 are used to place the location of the ck_edge transitions at approximately the median (half the transitions earlier, half the transitions later) of the transitions and place the clock center (ck_center) one half clock cycle away. The details for carrying out this operation are discussed in Alexander's paper and need not be repeated here.